Análise de desempenho de topologias de redes em chip (NoC)

AUTOR(ES)

Dino Macedo Amaral

DATA DE PUBLICAÇÃO

2008

RESUMO

The need to meet the existing demands in the microeletronic market has prompted designers to compact a big number of IP blocks in a small silicon area. From the pratical point of view, the distribuition of these IP blocks becomes a issue due to physical issues like high impedance caused by the number of wires that interconncet them, the power consupmtion to keep all IP blocks comunicating. An optimized occupation of the whole space used by the chip. In order to help the SoC designers , the concepts used in networking have been the main source to point out a possible solution for these situations. This paper shows the results of a benchmarck using gpNoCsim [18], which can help the NoC designers to find the bottlenecks when working with NoCs.

ASSUNTO(S)

latência microelectronics modelo analítico para roteamento network-on-chip throughput micro-eletrônica latency network-on-chip engenharia eletrica roteamento wormhole throughput analytical model wormhole routing

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