Memory Based Architectures
Mostrando 1-11 de 11 artigos, teses e dissertações.
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1. Um modelo de memória transacional para arquiteturas heterogêneas baseado em software Cache / A transactional memory model for heterogeneous architectures based in Software Cache
The adoption of multi-core processors by the industry has pushed towards the development of new techniques to simplify programming parallel software. The technique called transactional memories is one of the most promising. This technique is able to execute multiple tasks concurrently in an optimistic way to achieve a better performance. Another advantage is
Publicado em: 2010
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2. Explorando memoria transacional em software nos contextos de arquiteturas assimetricas, jogos computacionais e consumo de energia / Exploiting software transactional memory in the context of asymmetric architectures
The shift towards multicore processors taken by the semiconductor industry has initiated an era in which new languages, methodologies and tools are of paramount importance to the development of efficient concurrent systems that can be built in a timely way by all kinds of programmers. One of the main obstacles faced by programmers when dealing with shared me
IBICT - Instituto Brasileiro de Informação em Ciência e Tecnologia. Publicado em: 18/12/2009
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3. Proposal of two solutions to cope with the faulty behavior of circuits in future technologies
A diminuição no tamanho dos dispositivos nas tecnologias do futuro traz consigo um grande aumento na taxa de erros dos circuitos, na lógica combinacional e seqüencial. Apesar de algumas potenciais soluções começarem a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, ár
Publicado em: 2009
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4. Sequential and parallel approaches to reduce the data cube size.
Since the introduction of Data Warehouse (DW) and Online Analytical Processing (OLAP) technologies, efficient computation of data cubes has become one of the most relevant and pervasive problems in the DW area. The data cube operator has exponential complexity; therefore, the materialization of a data cube involves both huge amount of memory and substantial
Publicado em: 2009
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5. PBIW : um esquema de codificação baseado em padrões de instrução / PBIW : an encoding technique based on instruction patterns
Past works has shown that the increase of DRAM memory speed is not the same of processor speed. Even though, computer architecture researchers keep searching for new approaches to enhance the processor performance. In order to minimize this difference between the processor and memory speed, this work presents a new encoding technique based on encoded instruc
Publicado em: 2008
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6. Transactional memories : prototyping and simulation of hardware implementations and a characterization of the problem of contention management in software / Memorias transacionais : prototipagem e simulação de implementações em hardware e uma caracterização para o problema de gerenciamento de contenção em software
As parallel architectures become prevalent in the computer industry, more and more programmers are required to write parallel programs and are thus being exposed to the problems related to the use of traditional mechanisms for concurrency control. Transactional memory has been devised as a means for easing the burden of writing parallel Programs: the program
Publicado em: 2008
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7. Modelo Híbrido de Programação Paralela para uma Aplicação de Elasticidade Linear Baseada no Método dos Elementos Finitos
In the area of parallel processing there are two major programming paradigms: Shared Memory and Message Passing. Each of them fits into a specific physical model, but there are multiprocessor architectures whose mapping to one of these paradigms is not so simple. SMP clusters, for example, are built by connecting some shared memory machines through an interc
Publicado em: 2006
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8. Recurrent neural networks for prediction of short and long memory time series / Modelos de redes neurais recorrentes para previsão de series temporais de memorias curta e longa
Forecasting of time series is a topic of great interest nowadays. To do so, the data generating process needs to be estimated with a good degree of accuracy. In the last years, artificial neural networks are becoming more important in the statistical community. The more basic structure of a neural network, the feedforward neural nets, without feedback, can b
Publicado em: 2005
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9. Local DNA sequence alignment in a cluster of workstations: algorithms and tools
Distributed Shared Memory systems allow the use of the shared memory programming paradigm in distributed architectures where no physically shared memory exist. Scope consistent software DSMs provide a relaxed memory model that reduces the coherence overhead by ensuring consistency only at synchronization operations, on a per-lock basis. Much of the work in D
Journal of the Brazilian Computer Society. Publicado em: 2004-11
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10. Uma arquitetura para execução de codigo comprimido em sistemas dedicados
The demand for program memory in embedded systems has grown considerably in recent years, as a result of the need to accommodate new system functionalities such as novel user interfaces, additional hardware devices, etc. The increase in program size has turned memory into the largest single factor in the total area and power dissipation of a modern System-on
Publicado em: 2002
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11. Turbulent shallow-water model for orographic subgrid-scale perturbations
A parallel pseudo-spectral method for the simulation in distributed memory computers of the shallow-water equations in primitive form was developed and used on the study of turbulent shallow-waters LES models for orographic subgrid-scale perturbations. The main characteristics of the code are: momentum equations integrated in time using an accurate pseudo-sp
Journal of the Brazilian Society of Mechanical Sciences. Publicado em: 2000