Rfc 2544
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1. IMPLEMENTAÇÃO DE ARQUITETURAS DE PILHA UDP/IP EM HARDWARE RECONFIGURÁVEL BASEADO NO DESEMPENHO DE VAZÃO, LATÊNCIA E TAXA DE PERDA DE QUADROS / IMPLEMENTATION OF UDP/IP STACK ARCHITECTURES IN RECONFIGURABLE HARDWARE BASED ON THROUGHPUT, LATENCY AND FRAME LOSS RATE PERFORMANCE
This work presents the implementation of three architectures of UDP/IP network stack in reconfigurable hardware. Also, presents the development of a Tester based on the RFC 2544 methodology and implemented it in FPGA. This Tester was used to obtain the throughput, latency and frame loss rate results. The performance of the project shows, in average, throughp
Publicado em: 2010