Roteamento Wormhole
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1. Análise de desempenho de topologias de redes em chip (NoC)
The need to meet the existing demands in the microeletronic market has prompted designers to compact a big number of IP blocks in a small silicon area. From the pratical point of view, the distribuition of these IP blocks becomes a issue due to physical issues like high impedance caused by the number of wires that interconncet them, the power consupmtion to
Publicado em: 2008