Simulacao Em Nivel Logico
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1. NEW METHODOLOGY TO THE ESTIMATIVE OF CAPACITANCE AND POWER CONSUMPTION OF COMPLEX LOGIC GATES CMOS AT LOGIC LEVEL / NOVA METODOLOGIA PARA A ESTIMATIVA DE CAPACITÂNCIA E CONSUMO DE POTÊNCIA DE PORTAS LÓGICAS COMPLEXAS CMOS NO NÍVEL LÓGICO
This dissertation presents a methodology of capacitance estimation and power consumption in CMOS circuits combinational constituted basically of complex logic gates at logic level. The main objective in the development of this method is to provide a fast estimate of the power consumption of circuits at the logical design gates. Of this form, the considered m
Publicado em: 2005